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1/24 march 2005 m59pw064 64 mbit (4mb x16, uniform block) 3v supply lightflash? memory features summary mask-rom pin-out compatible supply voltage ?v cc = 2.7 to 3.6v for read ?v pp = 11.4 to 12.6v for program access time ? 90ns at v cc = 3.0 to 3.6v ? 100, 110ns at v cc = 2.7 to 3.6v programming time ? 9s per word typical ? multiple word programming option (8s typical chip program) suitable for on-board programming erase time ? 41s typical chip erase uniform blocks ? 32 blocks of 2 mbits program/erase controller ? embedded word program algorithms 10,000 program/erase cycles per block electronic signature ? manufacturer code: 0020h ? device code : 88aah figure 1. packages so44 (m) tsop48 (n) 12 x 20mm
m59pw064 2/24 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. so connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 multiple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 setup phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 program phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 verify phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 exit phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5. multiple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . 11
3/24 m59pw064 figure 5. multiple word program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v pp status bit (dq4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 multiple word program bit (dq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 status register bit dq1 is reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. data polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. data toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10.read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 11.write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. chip enable controlled, write ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12.so44 - 44 lead plastic small outline, 500 mils body width, package outline . . . . . . . . 20 table 13. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data . 20 figure 13.tsop48 - 48 lead plastic thin small outline, 12x20mm, package outline . . . . . . . . . . 21 table 14. tsop48 - 48 lead plastic thin small outline, 12x20mm, package mechanical data . . 21 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m59pw064 4/24 summary description the m59pw064 is a 64mbit (4mbx16), mask- rom pin-out compatible, non-volatile lightflash memory, that can be read, erased and reprogrammed. read operations can be performed using a single low voltage (2.7 to 3.6v) supply. program and erase operations require an additional v pp (11.4 to 12.6v) power supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the memory is divided into 32 uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased (see table 2., block addresses ). program and erase commands are written to the command interface of the memory. an on-chip program/erase con- troller (p/e.c.) simplifies the process of program- ming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the m59pw064 features an innovative command, multiple word program, that is used to program large streams of data. it greatly reduces the total programming time when a large number of words are written to the memory at any one time. using this command the entire memory can be pro- grammed in 8s, compared to 36s using the stan- dard word program. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. chip enable and output enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the memory is offered in so44 and tsop48 (12 x 20mm) packages. the memory is supplied with all the bits set to ?1?). figure 2. logic diagram table 1. signal names ai07230 22 a0-a21 dq0-dq15 v cc m59pw064 e v ss 16 g v pp a0-a21 address inputs dq0-dq15 data inputs/outputs e chip enable g output enable v cc supply voltage read v pp supply voltage program erase v ss ground nc not connected internally
5/24 m59pw064 figure 3. so connections figure 4. tsop connections g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 dq15 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 a19 a21 a4 a7 ai07231 m59pw064 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 a18 a20 v pp dq3 dq9 dq2 a6 dq0 a3 dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 dq4 dq5 a7 dq7 ai07268 m59pw064 12 1 13 24 25 36 37 48 dq8 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 a15 a14 v ss e a0 nc v pp a21 v ss v cc v ss a20 v ss v cc
m59pw064 6/24 table 2. block addresses block number address range 32 3e0000h-3fffffh 31 3c0000h-3dffffh 30 3a0000h-3bffffh 29 380000h-39ffffh 28 360000h-37ffffh 27 340000h-35ffffh 26 320000h-33ffffh 25 300000h-31ffffh 24 2e0000h-2fffffh 23 2c0000h-2dffffh 22 2a0000h-2bffffh 21 280000h-29ffffh 20 260000h-27ffffh 19 240000h-25ffffh 18 220000h-23ffffh 17 200000h-21ffffh 16 1e0000h-1fffffh 15 1c0000h-1dffffh 14 1a0000h-1bffffh 13 180000h-19ffffh 12 160000h-17ffffh 11 140000h-15ffffh 10 120000h-13ffffh 9 100000h-11ffffh 8 0e0000h-0fffffh 7 0c0000h-0dffffh 6 0a0000h-0bffffh 5 080000h-09ffffh 4 060000h-07ffffh 3 040000h-05ffffh 2 020000h-03ffffh 1 000000h-01ffffh block number address range
7/24 m59pw064 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the program controller. data inputs/outputs (dq0-dq7). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the command sent to the command interface of the program controller. when reading the status register they report the status of the ongoing algorithm. data inputs/outputs (dq8-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. chip enable (e ). the chip enable, e , activates the memory, allowing bus read operations to be performed. it also controls the bus write opera- tions, when v pp is in the v hh range. output enable (g ). the output enable, g , con- trols the bus read operations of the memory. it also allows bus write operations, when v pp is in the v hh range. v cc supply voltage. the v cc supply voltage supplies the power for read operations. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program opera- tions, i cc3 . v pp program supply voltage. v pp is both a power supply and write protect pin. the two func- tions are selected by the voltage range applied to the pin. when the v pp is in the v hh range (see table 10., dc characteristics , for the relevant values) the program/erase operation is enabled. during such operations the v pp must be stable in the v hh range. if the v pp is kept under the v hh range, particularly in the voltage range 0v to 3.6v, any program/ erase operation is disabled or stopped. note that v pp must not be left floating or uncon- nected as the device may become unreliable. v ss ground. the v ss ground is the reference for all voltage measurements.
m59pw064 8/24 bus operations there are six standard bus operations that control the device. these are bus read, bus write, out- put disable, standby, automatic standby and electronic signature. see table 3., bus opera- tions , for a summary. typically glitches of less than 5ns on chip enable or write enable are ig- nored by the memory and do not affect bus opera- tions. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs and applying a low signal, v il , to chip en- able and output enable. the data inputs/outputs will output the value, see figure 10., read ac waveforms , and table 11., read ac characteris- tics , for details of when the output becomes valid. bus write. bus write operations write to the command interface. bus write is enabled only when v pp is set to v hh . a valid bus write opera- tion begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable. the data inputs/outputs are latched by the command interface on the rising edge of chip enable. output enable must remain high, v ih , during the whole bus write operation. see figure 11., write ac waveforms, chip enable con- trolled , and table 12., chip enable controlled, write ac characteristics , for details of the timing requirements. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 10., dc characteristics . during program operation the memory will contin- ue to use the program supply current, i cc3 , for program operation until the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in table 3., bus operations , once the auto select command is executed. to exit electronic signature mode, the read/reset command must be issued. table 3. bus operations note: 1. x = v il or v ih . 2. xx = v il , v ih or v hh 3. when reading status register du ring program algorithm execution v pp must be kept at v hh . operation e g v pp address inputs a0-a21 data inputs/outputs dq15-dq0 bus read v il v il xx (3) cell address data output bus write v il v ih v hh command address data input output disable x v ih xx hi-z standby v ih xx x hi-z read manufacturer code v il v il v hh a0 = v il , a1 = v il , others v il or v ih 0020h read device code v il v il v hh a0 = v ih , a1 = v il , others v il or v ih 88aah
9/24 m59pw064 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. refer to tables 4 and 5 , for a summary of the com- mands. read/reset command. the read/reset command returns the memory to its read mode where it behaves like a rom or eprom, unless otherwise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. v pp must be set to v hh during the read/reset command. if v pp is set to either v il or v ih the com- mand will be ignored. the command can be is- sued, between bus write cycles before the start of a program operation, to return the device to read mode. once the program operation has started the read/reset command is no longer accepted. auto select command. the auto select command is used to read the manufacturer code and the device code. v pp must be set to v hh during the auto select com- mand. if v pp is set to either v il or v ih the com- mand will be ignored. three consecutive bus write operations are required to issue the auto se- lect command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued, all other commands are ignored. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . word program command. the word program command can be used to pro- gram a word to the memory array. v pp must be set to v hh during word program. if v pp is set to ei- ther v il or v ih the command will be ignored, the data will remain unchanged and the device will re- vert to read/reset mode. the command requires four bus write operations, the final write operation latches the address and data in the internal state machine and starts the p/e.c. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 6. . bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. multiple word program command the multiple word program command can be used to program large streams of data. it greatly reduces the total programming time when a large number of words are written in the memory at once. v pp must be set to v hh during multiple word program. if v pp is set either v il or v ih the com- mand will be ignored, the data will remain un- changed and the device will revert to read mode. it has four phases: the setup phase to initiate the command, the program phase to program the data to the memory, the verify phase to check that the data has been correctly programmed and re- program if necessary and the exit phase. setup phase. the multiple word program com- mand requires three bus write operations to ini- tiate the command (refer to table 4, multiple word program command and figure 8, multiple word program flowchart). the status register must be read in order to check that the p/e.c. has started (see table 7. and figure 6. ). program phase. the program phase requires n+1 bus write operations, where n is the number of words, to execute the programming phase (re- fer to table 5., multiple word program command , and figure 5., multiple word program flowchart ). before any bus write operation of the program phase, the status register must be read in order to check that the p/e.c. is ready to accept the op- eration (see table 7. and figure 6. ). the program phase is executed in three different sub-phases: 1. the first bus write operation of the program phase (the 4th of the command) latches the
m59pw064 10/24 start address and the first word to be programmed. 2. each subsequent bus write operation latches the next word to be programmed and automatically increments the internal address bus. it is not necessary to provide the address of the location to be programmed but only a continue address, ca (a17 to a21 equal to the start address), that indicates to the pc that the program phase has to continue. a0 to a16 are ?don?t care?. 3. finally, after all words have been programmed, a bus write operation (the (n+1) th ) with a final address, fa (a17 or a higher address pin different from the start address), ends the program phase. the memory is now set to enter the verify phase. verify phase. the verify phase is similar to the program phase in that all words must be resent to the memory for them to be checked against the programmed data. before any bus write operation of the verify phase, the status register must be read in order to check that the p/e.c. is ready for the next oper- ation or if the reprogram of the location has failed (see table 7. and figure 6. ). three successive steps are required to execute the verify phase of the command: 1. the first bus write operation of the verify phase latches the start address and the word to be verified. 2. each subsequent bus write operation latches the next word to be verified and automatically increments the internal address bus. as in the program phase, it is not necessary to provide the address of the location to be programmed but only a continue address, ca (a17 to a21 equal to the start address). 3. finally, after all words have been verified, a bus write cycle with a final address, fa (a17 or a higher address pin different from the start address) ends the verify phase. exit phase. after the verify phase ends, the sta- tus register must be read to check if the command has successfully completed or not (see table 7. and figure 6. ). if the verify phase accomplishes successfully, the memory returns to the read mode and dq6 stops toggling. on the contrary, if the p/e.c. fails to reprogram a given location, the verify phase terminates, dq6 continues toggling and error bit dq5 is set in the status register. if the error is due to a v pp failure dq4 is also set. when the operation fails a read/reset command must be issued to return the device to read mode. during the multiple word program operation the memory will ignore all commands. it is not possible to issue any command to abort or pause the oper- ation. typical program times are given in table 6. . bus read operations during the program opera- tion will output the status register on the data in- puts/outputs. see the section on the status register for more details. note that the multiple word program command cannot change a bit set at ?0? back to ?1?. block erase command. the block erase command can be used to erase a block. it sets all of the bits in the block to ?1?. all previous data in the block is lost. v pp must be set to v hh during block erase. if v pp is set to either v il or v ih the command will be ig- nored, the data will remain unchanged and the de- vice will revert to read/reset mode. six bus write operations are required to select the block . the block erase operation starts the p/e.c. after the last bus write operation. the status reg- ister can be read after the sixth bus write opera- tion. see the status register for details on how to identify if the p/e.c. has started the block erase operation. during the block erase operation the memory will ignore all commands. typical block erase times are given in table 6. . all bus read operations dur- ing the block erase operation will output the sta- tus register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. chip erase command. the chip erase command can be used to erase the entire memory. it sets all of the bits in the mem- ory to ?1?. all previous data in the memory is lost. v pp must be set to v hh during chip erase. if v pp is set to either v il or v ih the command will be ig- nored, the data will remain unchanged and the de- vice will revert to read/reset mode. six bus write operations are required to issue the chip erase command and start the p/e.c. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 6. . all bus read opera- tions during the chip erase operation will output
11/24 m59pw064 the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. table 4. standard commands note: x don?t care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal . the command interface only uses a0-a10 and dq0-dq7 to verify the commands; a11-a21, dq8-dq15 are don?t care. table 5. multiple word program command note: a bus read must be done between each write cycle where the data is programmed or verified, to read the status register and check that the memory is ready to accept the next data. sa is the start address. ca is the continue address. fa is the final address. x don?t care, n = number of words to be programmed. table 6. program, erase times and program, erase endurance cycles note: 1. t a = 25c, v pp = 12v. command length bus write operations 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 word program 4 555 aa 2aa 55 555 a0 pa pd block erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 phase length bus write operations 1st 2nd 3rd 4th 5th nth final add data add data add data add data add data add data add data set-up 3 555 aa 2aa 55 555 20 program n+1 sa pd1 ca pd2 ca pd3 ca pd4 ca pd5 ca pan fa x verify n+1 sa pd1 ca pd2 ca pd3 ca pd4 ca pd5 ca pan fa x parameter min typ (1) typical after 10k w/e cycles (1) max unit chip erase 41 44 120 s block erase (128 kwords) 1.5 6 s program (word) 9 200 s chip program (multiple word) 8 144 s chip program (word by word) 36 144 s program/erase cycles (per block) 10,000 cycles
m59pw064 12/24 figure 5. multiple word program flowchart write aah address 555h ai05954b start read status register yes no dq0 = 0? write 55h address 2aah write 20h address 555h write data1 start address write data 2 continue address yes no read status register write data n continue address yes no read status register write xx final address read status register no write data1 start address write data 2 continue address no read status register write data n continue address read status register write xx final address yes write f0h address xx exit (read mode) dq0 = 0? dq0 = 0? dq0 = 0? dq0 = 0? dq0 = 0? read status register no dq6 toggling? dq4 = 0? yes fail, v pp error no program phase yes no dq0 = 0? yes setup time exceeded? exit ( setup failed ) no dq0 = 0? read status register no yes yes no dq5 = 1? yes no dq5 = 1? yes dq6 toggling? read status register no yes yes no fail error yes no setup phase verify phase exit phase read status register dq5 = 1 ?
13/24 m59pw064 status register bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 7., status register bits . data polling bit (dq7). the data polling bit can be used to identify whether the p/e.c. has suc- cessfully completed its operation. the data poll- ing bit is output on dq7 when the status register is read. during a word program operation the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the word program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts ?0?, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. figure 6., data polling flowchart , gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the p/e.c. has successfully com- pleted its operation. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. figure 7., data toggle flowchart , gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the p/e.c. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that ad- dress will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. v pp status bit (dq4). the v pp status bit can be used to identify if any program or erase operation has failed due to a v pp error. if v pp falls below v hh during any program or erase operation, the oper- ation aborts and dq4 is set to ?1?. if v pp remains at v hh throughout the program or erase operation, the operation completes and dq4 is set to ?0?. erase timer bit (dq3). the erase timer bit can be used to identify the start of p/e.c. operation during a block erase command. once the p/e.c. starts erasing the erase timer bit is set to ?1?. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the p/e.c. dur- ing block erase operations. the alternative tog- gle bit is output on dq2 when the status register is read. during block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the block being erased. once the operation completes the memory returns to read mode. after an erase operation that causes the error bit to be set, the alternative toggle bit can be used to identify where the error occurred. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within a block that has not erased correctly. the alternative toggle bit does not change if the ad- dressed block has erased correctly. multiple word program bit (dq0). the multiple word program bit can be used to indicate whether the p/e.c. is active or inactive during multiple word program. when the p/e.c. has written one word and is ready to accept the next word, the bit is set to ?0?. status register bit dq1 is reserved.
m59pw064 14/24 table 7. status register bits note: 1. unspecified data bits should be ignored. 2. dq4 = 0 if v pp v hh during program/erase algorithm execution; dq4 = 1 if v pp < v hh during program/erase algorithm execution. figure 6. data polling flowchart figure 7. data toggle flowchart command (1) p/e.c. status address dq7 dq6 dq5 dq4 dq3 dq2 dq0 multiple word program programming ? ? toggle 0 ? 0 ? 1 waiting for data ? ? toggle 0 ? 0 ? 0 program fail ? ? toggle 1 (2) 0?1 word program programming ? dq7 toggle0?0 ? ? program error ? dq7 tog gle 1 (2) 0?? chip erase/ block erase erasing in erasing block 0 toggle 0 ? 1 toggle ? not in erasing block 0 toggle 0 ? 1 no toggle ? erase fail in failed block 0 toggle 1 (2) 1 toggle ? not in failed block 0 toggle 1 (2) 1 no toggle ? read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
15/24 m59pw064 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 8. absolute maximum ratings note: 1. minimum voltage may undershoot to ?2v for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v for less than 20ns during transitions. 3. maximum voltage may overshoot to 14.0v for less than 20ns during transitions. v pp must not remain at v hh for more than a total of 80hrs. symbol parameter min max unit t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c v io input or output voltage (1,2) ?0.6 v cc +0.6 v v cc read supply voltage ?0.6 4 v v pp program/erase supply voltage (3) ?0.6 13.5 v
m59pw064 16/24 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 9., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 9. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit device capacitance note: sampled only, not 100% tested. parameter m59pw064 unit 100, 110 min max v cc read supply voltage 2.7 3.6 v v pp program/erase supply voltage 11.4 12.6 v ambient operating temperature (t a ) 070c load capacitance (c l ) 30 pf input rise and fall times 10 ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v ai05546 3v 0v 1.5v ai05447 1.3v out c l c l = 30pf c l includes jig capacitance 3.3k ? 1n914 device under test symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
17/24 m59pw064 table 10. dc characteristics note: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. average value. symbol parameter (1) test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 (2) supply current (standby) e = v cc 0.2v 100 a i cc3 supply current (program) p/e.c. active 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ?100 a v cc ?0.4 v v hh v pp program voltage 11.4 12.6 v i hh v pp current (program) p/e.c. active 10 ma
m59pw064 18/24 figure 10. read ac waveforms table 11. read ac characteristics note: 1. v pp must be applied after v cc and with the chip enable (e ) at v ih . 2. sampled only, not 100% tested. symbol alt parameter (1) test condition m59pw064 unit 100 110 v cc =3.0to 3.6v v cc = 2.7 to 3.6v v cc = 2.7 to 3.6v t avqv t acc address valid to output valid e = v il , g = v il max 90 100 110 ns t elqv t ce chip enable low to output valid g = v il max 90 100 110 ns t glqv t oe output enable low to output valid e = v il max 35 35 35 ns t ehqz (2) t hz chip enable high to output hi-z g = v il max 30 30 30 ns t ghqz (2) t df output enable high to output hi-z e = v il max 30 30 30 ns t axqx t oh address transition to output transition min000ns ai07232 tavqv taxqx tehqz tglqv valid a0-a21 g dq0-dq15 e telqv tghqz valid
19/24 m59pw064 figure 11. write ac waveforms, chip enable controlled table 12. chip enable controlled, write ac characteristics note: 1. t a = 25c; v pp = 11.4 to 12.6v; v cc = 2.7 to 3.6v. v pp must be applied after v cc and with the chip enable (e ) at v ih . sampled only, not 100% tested. 2. not required in auto select or read/reset command sequences. symbol alt parameter (1) m59pw064 unit t eleh t cp chip enable low to chip enable high min 50 ns t dveh t ds input valid to chip enable high min 50 ns t ehdx t dh chip enable high to input transition min 0 ns t ehel t cph chip enable high to chip enable low min 50 ns t avel t as address valid to chip enable low min 0 ns t elax t ah chip enable low to address transition min 100 ns t ghel output enable high chip enable low min 10 ns t ehgl t oeh chip enable high to output enable low min 10 ns t vchel t vcs v cc high to chip enable low min 50 s t vphel (2) t vcs v pp high to chip enable low min 500 ns ai07233 e g a0-a21 dq0-dq15 valid valid v cc tvchel tehel tavel tehgl telax tehdx tdveh teleh tghel v pp tvphel
m59pw064 20/24 package mechanical figure 12. so44 - 44 lead plastic small outline, 500 mils body width, package outline note: drawing is not to scale. table 13. so44 - 44 lead plastic small outline, 500 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a3.000.118 a1 0.10 0.004 a2 2.69 2.56 2.79 0.106 0.101 0.110 b 0.35 0.50 0.014 0.020 c 0.18 0.28 0.007 0.011 d 28.50 28.37 28.63 1.122 1.117 1.127 ddd 0.10 0.004 e 16.03 15.77 16.28 0.631 0.621 0.641 e1 12.60 12.47 12.73 0.496 0.491 0.501 e 1.27 ? ? 0.050 ? ? l 0.79 0.031 l1 1.73 0.068 8 8 n44 44 e1 44 e d c e 1 22 23 b so-f l a1 a ddd a2 l1
21/24 m59pw064 figure 13. tsop48 - 48 lead plastic thin small outline, 12x20mm, package outline note: drawing is not to scale. table 14. tsop48 - 48 lead plastic thin small outline, 12x20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 305305 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
m59pw064 22/24 part numbering table 15. ordering information scheme note: 1. this speed also guarantees 90ns access time at v cc = 3.0 to 3.6v. devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m59p064 100 m 1 t device type m59p = lightflash memory operating voltage w = v cc = 2.7 to 3.6v device function 064 = 64 mbit (x16) speed 100 = 100 ns (1) 110 = 110 ns package m = so44, 500mils body width n = tsop48: 12 x 20 mm temperature range 1 = 0 to 70 c option t = tape & reel packing
23/24 m59pw064 revision history table 16. document revision history date version revision details 19-jul-2002 1.0 first issue 05-aug-2002 1.1 multiple word program command table clarified ( table 5. ) i cc1 , i cc2 clarified ( table 10. ) 28-nov-2002 1.2 so44 body width modified bus operation table clarified ( table 3. ) read/reset, auto select and multiple word program commands clarified mask-rom pin-out compatible feature added 90ns speed class obtained from the 100ns at v cc = 3.0 to 3.6v (tables 11 and 12 ) chip enable, output enable, program supply voltage clarified 07-feb-2003 1.3 document status changed to datasheet 30-jan-2004 2.0 tsop48 package specifications changed (see figure 13. and table 14. ). 15-mar-2005 3.0 table 15., ordering information scheme corrected.
m59pw064 24/24 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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